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300/sec Yaw Rate Gyro with SPI Interface ADIS16100
FEATURES
Complete angular rate gyroscope Z-axis (yaw rate) response SPI(R) digital output interface High vibration rejection over wide frequency 2000 g powered shock survivability Externally controlled self test Internal temperature sensor output Dual auxiliary 12-bit ADC inputs Absolute rate output for precision applications 5 V single-supply operation 8.2 mm x 8.2 mm x 5.2 mm package
GENERAL DESCRIPTION
The ADIS16100 is a complete angular rate sensor (gyroscope) that uses the Analog Devices surface-micromachining process to make a functionally complete angular rate sensor with an integrated serial peripheral interface (SPI). The digital data available at the SPI port is proportional to the angular rate about the axis normal to the top surface of the package (see Figure 19). A single external resistor can be used to increase the measurement range. An external capacitor can be used to lower the bandwidth. Access to an internal temperature sensor measurement is provided, through the SPI, for compensation techniques. Two pins are available to the user to input analog signals for digitization. An additional output pin provides a precision voltage reference. Two digital self-test inputs electromechanically excite the sensor to test operation of the sensor and the signal conditioning circuits. The ADIS16100 is available in an 8.2 mm x 8.2 mm x 5.2 mm, 16-terminal, peripheral land grid array (LGA) package.
APPLICATIONS
Platform stabilization Image stabilization Guidance and control Inertial measurement units
FUNCTIONAL BLOCK DIAGRAM
COUT FILT RATE
ADIS16100
300/s GYROSCOPE MUX/ADC 4-CHANNEL SPI
SCLK DIN CS DOUT
TEMP SENSOR AIN2 AIN1 VREF REF
COM ST1 ST2 VCC +5V VDRIVE +3V TO +5V
05461-001
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADIS16100 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 4 Timing Specifications............................... ....................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Supply and Common Considerations ..................................... 11 Increasing Measurement Range ............................................... 11 Setting Bandwidth...................................................................... 11 Self-Test Function ...................................................................... 11 Continuous Self Test .................................................................. 11 Control Register ......................................................................... 12 Serial Interface ............................................................................ 13 Rate Sensitive Axis ..................................................................... 13 Second-Level Assembly ............................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
5/06--Rev. 0 to Rev. A Changes to Table 1............................................................................ 4 Changes to Setting Bandwidth Section........................................ 11 Changes to Table 9 and Table 10................................................... 13 1/06--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADIS16100 SPECIFICATIONS
TA = 25C, VCC = VDR = 5 V, angular rate = 0/sec, COUT = 0 F, 1 g, unless otherwise noted. Table 1.
Parameter SENSITIVITY Dynamic Range 2 Initial Change Over Temperature 3 Nonlinearity NULL Initial Null Change Over Temperature3 Turn-On Time Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Rate Noise Density FREQUENCY RESPONSE 3 dB Bandwidth (User-Selectable) 4 Sensor Resonant Frequency SELF-TEST INPUTS ST1 RATEOUT Response 5 ST2 RATEOUT Response5 Logic 1 Input Voltage Logic 0 Input Voltage Input Impedance TEMPERATURE SENSOR Reading at 298 K Scale Factor 2.5 V REFERENCE Voltage Value Load Drive to Ground Load Regulation Power Supply Rejection Temperature Drift LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN ANALOG INPUTS 6 Resolution Integral Nonlinearity6 Differential Nonlinearity Offset Error Gain Error Input Voltage Range Leakage Current Input Capacitance Full Power Bandwidth Conditions Clockwise rotation is positive output Full-scale range over specifications range @ 25C VCC = VDRIVE = 4.75 V to 5.25 V Best fit straight line Min 1 300 3.68 Typ Max1 Unit /sec LSB//sec % % of FS LSB LSB ms LSB/g LSB/V LSB rms LSB rms/Hz Hz kHz -376 +376 1.7 50 2048 6.88 2.45 Source 0 A < IOUT < 100 A VCC = VDRIVE = 4.75 V to 5.25 V Delta from 25C 0.7 x VDRIVE Typically 10 nA All at TA = -40C to +85C 12 -2 -2 -8 -2 0 -1 20 8 +2 +2 +8 +2 VREF x 2 +1 Bits LSB LSB LSB %FSR V A pF MHz -1 10 0.3 x VDRIVE +1 2.5 100 5.0 1.0 5.0 2.55 LSB LSB V V k LSB LSB/K V A mV/mA mV/V mV V V A pF
4.1 10 0.15 2048 205 75 0.82 4.1 3.25 0.43 40 14
4.52
1876 VCC = VDR = 4.75 V to 5.25 V Power on to 1/2/sec of final Any axis VCC = VDRIVE = 4.75 V to 5.25 V 0.1 Hz to 40 Hz f = 100 Hz COUT = 0 F
2200
ST1 pin from Logic 0 to Logic 1 ST2 pin from Logic 0 to Logic 1 Standard high logic level definition Standard low logic level definition To common
-121 +121 3.3
-221 +221
Proportional to absolute temperature
Rev. A | Page 3 of 16
ADIS16100
Parameter DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) CONVERSION RATE Conversion Time Throughput Rate POWER SUPPLY VCC VDRIVE VCC Quiescent Supply Current VDRIVE Quiescent Supply Current Power Dissipation
1 2
Conditions ISOURCE = 200 A ISINK = 200 A 16 SCLK cycles with SCLK at 20 MHz All at TA = -40C to +85C
Min 1 VDRIVE - 0.2
Typ
Max1
Unit V V ns MSPS V V mA A mW
0.4 800 1 4.75 2.7 5 7.0 70 40 5.25 5.25 9.0 500
VCC @ 5 V, fSCLK = 50 kSPS VDRIVE @ 5 V, fSCLK = 50 kSPS VCC and VDRIVE @ 5 V, fSCLK = 50 kSPS
All minimum and maximum specifications are guaranteed. Typical specifications are neither tested nor guaranteed. Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 V supplies. 3 Defined as the output change from ambient to maximum temperature or ambient to minimum temperature. 4 Frequency at which the response is 3 dB down from dc response. Bandwidth = 1/(2 x x 180 k x (22 nF + COUT)). For COUT = 0, bandwidth = 40 Hz. For COUT = 1 F, bandwidth = 0.87 Hz. 5 Self-test response varies with temperature. 6 For VIN < VCC.
TIMING DIAGRAM
CS
t2
SCLK 1 2 3 4
t6
5
tCONVERT
6 11 12 13
B
14 15 16
t3
ZERO DOUT THREE-STATE ZERO t
9
t4
ADD1 ADD0 DB11 2 IDENTIFICATION BITS DONTC DONTC ADD1
t7
DB10 DB4 DB3 DB2
t5 t8
DB1 DB0
t11 tQUIET
THREE-STATE
05461-002
t10
ADD0 CODING DONTC DONTC DONTC DONTC
DIN
WRITE
LOW
Figure 2. Gyroscope Serial Interface Timing Diagram
The DIN bit functions are outlined in the following table (see the Control Register section for additional information).
Table 2. DIN Bit Functions
MSB (11) WRITE LOW DONTC DONTC ADD1 ADD0 HIGH HIGH DONTC DONTC LOW LSB (0) CODING
Rev. A | Page 4 of 16
ADIS16100 TIMING SPECIFICATIONS
TA = 25C, angular rate = 0/sec, unless otherwise noted. 1 Table 3.
Parameter fSCLK 2 tCONVERT tQUIET t2 t3 3 t43 t5 t6 t7 t8 4 t9 t10 t11 t12
1
VCC = VDR = 5 10 20 16 x tSCLK 50 10 30 40 0.4 x tSCLK 0.4 x tSCLK 10 15/35 10 5 20 1
Unit kHz min MHz max ns min ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min s max
Description
Minimum quiet time required between CS rising edge and start of next conversion CS to SCLK setup time Delay from CS until DOUT three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to DOUT valid hold time SCLK falling edge to DOUT high impedance DIN setup time prior to SCLK falling edge DIN hold time after SCLK falling edge 16th SCLK falling edge to CS high Power-up time from full power-down/auto shutdown modes
Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 V x VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200A
IOL
TO OUTPUT PIN
1.6V CL 50pF 200A IOH
05461-003
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 5 of 16
ADIS16100 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) +VCC to COM +VDRIVE to COM Analog Input Voltage to COM Digital Input Voltage to COM Digital Output Voltage to COM STx Input Voltage to COM Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g -0.3 V to +6.0 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -0.3 V to +7.0 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -40C to +85C -65C to +150C
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Drops onto hard surfaces can cause shocks of greater than 2000 g and exceed the absolute maximum rating of the device. Care should be exercised in handling to avoid damage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 16
ADIS16100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDRIVE RATE AIN1
8 9
5
6
FILT
7
NC
4
AIN2
ADIS16100
DOUT
3 10
BOTTOM VIEW (Not to Scale)
2 11
COM
SCLK
VREF
DIN
1 16 15 14 13
12
ST2
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
Mnemonic DIN SCLK DOUT NC RATE FILT VDRIVE AIN1 AIN2 COM VREF ST2 ST1 VCC NC CS
Type 1 I I O
O I S I I S O I I S I
Description Data In. Data to be written to the control register is provided on this input and is clocked in on the falling edge of the SCLK. Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data to the control registers. Also used as a clock source for the ADIS16100 conversion process. Data Out. The data on this pin represents data being read from the control registers and is clocked on the falling edge of the SCLK. No Connect. Buffered analog output representing the angular rate signal. External capacitor connection to control bandwidth. Power to SPI. The voltage supplied to this pin determines the voltage at which the serial interface operates. External Analog Input Channel 1. Single-ended analog input multiplexed into the on-chip trackand-hold according to the setting of the ADD0 and ADD1 address bits. External Analog Input Channel 2. Single-ended analog input multiplexed into the on-chip trackand-hold according to the setting of the ADD0 and ADD1 address bits. Common. Reference point for all circuitry in the ADIS16100. Precision 2.5 V Reference. Self Test Input 2. Self Test Input 1. Analog Power. No Connect. Chip Select. Active low. This input frames the serial data transfer and initiates the conversion process.
I = Input; O = Output; S = Power supply.
Rev. A | Page 7 of 16
05461-020
VCC
ST1
NC
CS
ADIS16100 TYPICAL PERFORMANCE CHARACTERISTICS
30
60
PERCENT OF POPULATION (%)
20
PERCENT OF POPULATION (%)
25
50
40
15
30
10
20
5
05461-004
10
05461-007
0 1845 1895 1945 1995 2045 2095 2145 2195 2245 NULL (LSB)
0 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 SUPPLY CURRENT (mA)
Figure 5. Initial Null Histogram
2250 2200
PERCENT OF POPULATION (%)
Figure 8. Supply Current Histogram
80 70 60 50 40 30 20
05461-008
2150
NULL LEVEL (LSB)
2100 +85C 2050 2000 1950 -40C
05461-005
+25C
1900 1850 4.7
10 0 -371 -346 -321 -296 -271 -246 -221 -196 -171 -146 -121 ST1 (LSB)
4.8
4.9
5.0 VCC (V)
5.1
5.2
5.3
Figure 6. Null Level vs. Supply Voltage
2040 30 PART AVERAGE, 30 PART AVERAGE, 30 PART AVERAGE, VCC = 4.75V VCC = 5V VCC = 5.25V
PERCENT OF POPULATION (%)
Figure 9. Self Test 1 Histogram
80 70 60 50 40 30 20
05461-009
2030
2020
NULL LEVEL (LSB)
2010
2000 1990
05461-006
1980 1970 -50
10 0 121 146 171 196 221 246 271 296 321 346 371 ST2 (LSB)
-20
10
40
70
100
TEMPERATURE (C)
Figure 7. Null Level vs. Temperature
Figure 10. Self Test 2 Histogram
Rev. A | Page 8 of 16
ADIS16100
0 -50
SELF-TEST LEVEL (LSB) SELF-TEST LEVEL (LSB)
250 240 230
-100 -150 -200 -250 +25C +85C -300
05461-011
220 210 200 190 180 170 160 150 -50 -20 10 40 70
05461-012
-40C
30 PART AVERAGE, 30 PART AVERAGE, 30 PART AVERAGE,
VCC = 4.75V VCC = 5V VCC = 5.25V
-350 -400 4.7
4.8
4.9
5.0 VCC (V)
5.1
5.2
5.3
100
TEMPERATURE (C)
Figure 11. Self Test 1 vs. Supply Voltage
400 350
SELF-TEST LEVEL (LSB)
Figure 14. Self Test 2 vs. Temperature
3 30 PART AVERAGE, 30 PART AVERAGE, 30 PART AVERAGE, 2
OFFSET LEVEL (LSB)
VCC = 4.75V VCC = 5V VCC = 5.25V
300 +85C 250 200 150 100 -2
05461-010 05461-014
+25C
1
0
-40C
-1
50 0 4.7
4.8
4.9
5.0 VCC (V)
5.1
5.2
5.3
-3 -50
-20
10
40
70
100
TEMPERATURE (C)
Figure 12. Self Test 2 vs. Supply Voltage
-150 -160 -170
SELF-TEST LEVEL (LSB) GAIN ERROR (LSB)
Figure 15. ADC Offset vs. Temperature and Supply Voltage
3 30 PART AVERAGE, VCC = 4.75V 30 PART AVERAGE, VCC = 5V 30 PART AVERAGE, VCC = 5.25V
30 PART AVERAGE, VCC = 4.75V 30 PART AVERAGE, VCC = 5V 30 PART AVERAGE, VCC = 5.25V
2
-180 -190 -200 -210 -220 -230 -240 -250 -50 -20 10 40 70
05461-013
1
0
-1
-2
05461-015
100
-3 -50
-20
10
40
70
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Self Test 1 vs. Temperature
Figure 16. ADC Gain Error vs. Temperature (Excluding VREF)
Rev. A | Page 9 of 16
ADIS16100
2.500 2.499 2.498 +25C 2.497
VREF LEVEL (V)
2060
2055 +85C
XXX (X)
05461-016
2.496 2.495 -40C 2.494 2.493 2.492 2.491 2.490 4.7 4.8 4.9 5.0 VCC (V) 5.1 5.2 5.3
2050
2045
2040 0 1000 2000 3000 4000 5000 6000 7000 8000 1 0 5 9 339 1307 4132 1996 387 12 3 1
Figure 17. VREF vs. Supply Voltage
000001111111011X 000001111111100X 000001111111101X 000001111111110X 000001111111111X 000010000000000X 000010000000001X 000010000000010X 0000100000000 11X 000010000000100X 000010000000101X 000010000000 110X SAMPLES = 8192, SPREAD = 23, STD DEV = 1.695, MEAN = 2050.682
Figure 18. Noise Histogram
Rev. A | Page 10 of 16
05461-017
ADIS16100 THEORY OF OPERATION
The ADIS16100 operates on the principle of a resonator gyro. Two polysilicon sensing structures each contain a dither frame, which is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force during angular rate. At two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers that are placed between fixed pickoff fingers to form a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The rate signal is then converted to a digital representation of the output on the SPI pins. The dual-sensor design rejects external g-forces and vibration. Fabricating the sensor with the signal conditioning electronics preserves signal integrity in noisy environments. The electrostatic resonator requires 14 V to 16 V for operation. Because only 5 V is typically available in most applications, a charge pump is included on-chip. After the demodulation stage, there is a single-pole, low-pass filter included on-chip that is used to limit high frequency artifacts before final amplification. A second single-pole, lowpass filter is set up via the bandwidth limit capacitor, COUT. This pole acts as the primary filter within the system (see the Increasing Measurement Range section). The trade-off associated with increasing the full-scale range are potential increase in output null drift (as much as 2/sec over temperature) and introducing initial null bias errors that must be calibrated.
SETTING BANDWIDTH
The ADIS16100 provides the ability to reduce the bandwidth. This important feature enables a simple method for achieving optimal bandwidth/noise trade-offs. An external capacitor can be used in combination with an on-chip resistor to create a lowpass filter to limit the bandwidth of the ADIS16100's rate response. The -3 dB frequency is defined as
f OUT = 1/ (2 x x ROUT x (COUT + 0.022 F ))
where ROUT represents an internal impedance that was trimmed during manufacturing to 180 k 1%. Any external resistor applied between the RATE pin and the FILT pin results in
ROUT = (180 k x R EXT ) / (180 k + R EXT )
With COUT = 0 F, a default -3 dB frequency response of 40 Hz is obtained, based upon an internal 0.022 F capacitor implemented on-chip.
SUPPLY AND COMMON CONSIDERATIONS
Power supply noise and transient behaviors can influence the accuracy and stability of any sensor-based measurement system. When considering the power supply for the ADIS16100, it is important to understand that the ADIS16100 provides 0.2 F of decoupling capacitance on the VCC pin. Depending on the level of noise present in the system power supply, the ADIS16100 may not require any additional decoupling capacitance for this supply. The analog supply, VCC, and the digital drive supply, VDRIVE, are segmented to allow multiple logic levels to be used in receiving the digital output data. VDRIVE is intended for the down-stream logic power supply and supports standard 3.3 V and 5 V logic families. The VDRIVE supply does not have internal decoupling capacitors.
SELF-TEST FUNCTION
The ADIS16100 includes a self-test feature that actuates each of the sensing structures and associated electronics in the same manner, as if subjected to angular rate. It provides a simple method for exercising the mechanical structure of the sensor, along with the entire signal processing circuit. It is activated by standard logic high levels applied to Input ST1, Input ST2, or both. ST1 causes a change in the digital output equivalent to typically -221 LSB, and ST2 causes an opposite +221 LSB change. The self-test response follows the viscosity temperature dependence of the package atmosphere, approximately 0.25%/C. Activating both ST1 and ST2 simultaneously is not damaging. Because ST1 and ST2 are not necessarily closely matched, actuating both simultaneously can result in an apparent null bias shift.
INCREASING MEASUREMENT RANGE
The full-scale measurement range of the ADIS16100 is increased by placing an external resistor between the RATE pin and the FILT pin. This external resistor would be in parallel with an internal 180 k, 1% resistor. For example, a 330 k external resistor gives ~50% increase in the full-scale range. This is effective for up to a 4x increase in the full-scale range (minimum value of the parallel resistor allowed is 45 k). The internal circuitry headroom requirements prevent further increase in the linear full-scale output range.
CONTINUOUS SELF TEST
As an additional failure detection measure, power-on self test can be performed. However, some applications warrant a continuous self test-while-sensing rate.
Rev. A | Page 11 of 16
ADIS16100
CONTROL REGISTER
The control register on the ADIS16100 is a 12-bit, write-only register. Data is loaded from the DIN pin on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line dictates the configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. Table 8 shows the analog input channel selection options. Table 6. Channel Selection
ADD1 0 0 1 1 ADD0 0 1 0 1 Analog Input Channel Gyroscope Temperature sensor AIN1 input AIN2 input
Table 7. The DIN Bit Stream
MSB (11) WRITE LOW DONTC DONTC ADD1 ADD0 HIGH HIGH DONTC DONTC LOW LSB (0) CODING
Table 8. Analog Input Channel Selection Options
Bit 11 Mnemonic WRITE Comment The value written to this bit of the control register determines whether the following 11 bits are loaded to the control register or not. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged. This bit should be held low. Don't care. These two address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted in the next serial transfer. The selected input channel is decoded as shown in Table 6. The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next channel to be converted is selected by the mux on the 14th SCLK falling edge. These pins should be held high. Don't care. This bit should be held low. This bit selects the type of output coding used for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion).
10 9, 8 7, 6
LOW DONTC ADD1, ADD0
5, 4 3, 2 1 0
HIGH DONTC LOW CODING
Rev. A | Page 12 of 16
ADIS16100
SERIAL INTERFACE
Figure 2 shows the detailed timing diagram for the serial interface to the ADIS16100. The chip select signal, CS, frames the entire data transfer, because it must be kept in a Logic 0 state to communicate with the ADIS16100. The serial clock, SCLK, provides the conversion clock and controls the transfer of information to and from the ADIS16100 during each conversion cycle. The data input, DIN, provides access to critical control parameters in the control register, and the output signal, DOUT, provides access to the output data of the ADIS16100. The ADIS16100 offers an efficient data transfer function by supporting simultaneous READ and WRITE cycles. A data transfer cycle is started when the CS transitions to a Logic 0 state. If DIN is in Logic 1 state during the first falling edge of the SCLK, then the next 11 SCLK cycles fill the control register with the contents on the DIN pin. The appropriate bit definitions for DIN can be found in Table 7 and Table 8. If the DIN is in a Logic 0 state during the first falling edge of the SCLK, then contents of the control register remain unchanged. Because the control register is only 12-bits wide, the contents on the DIN pin during the last four SCLK cycles are ignored. During this same cycle, the digital output data is clocked out on the DOUT pin, with the bit transitions occurring shortly after the SCLK falling edges. The DOUT bit sequence is characterized in Table 9 and Table 10. On the 16th falling edge of SCLK, the DOUT line goes back into a three-state mode. If the rising edge of CS occurs before 16 SCLKs have elapsed, the DOUT line goes back into three-state mode and the control register is not updated. Otherwise, DOUT returns to a three-state mode on the 16th SCLK falling edge, as shown in Figure 2.
RATE SENSITIVE AXIS
This is a z-axis rate-sensing device that is also called a yaw rate sensing device. It produces a positive going output voltage for clockwise rotation about the axis normal to the package top, that is, clockwise when looking down at the package lid.
RATE AXIS LONGITUDINAL AXIS VCC = 5V 4.75V 2.5V RATE IN 0.25V LATERAL AXIS GND
05461-019
RATE
A1
Figure 19. Rate Signal Increases with Clockwise Rotation
Table 9. DOUT Bit Stream
SCLK1 LOW LOW ADD1 ADD0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 SCLK16 DB0
Table 10. DOUT Bit Functions
SCLK 1, 2 3, 4 5 6 to 15 16 Mnemonic LOW ADD1, ADD0 DB11 DB10 to DB1 DB0 Comment The outputs are low for SCLK1 and SCLK2. The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. See Table 6 for the coding of these address bits. Data Bit 11 (MSB). Data Bit 10 to Data Bit 1. Data Bit 0 (LSB).
Rev. A | Page 13 of 16
ADIS16100
SECOND-LEVEL ASSEMBLY
The recommended pad geometries for the ADIS16100 are displayed in Figure 20. The ADIS16100 can be attached to printed circuit boards using Sn63 or an equivalent solder. Figure 21 and Table 11 provide recommended solder reflow profiles for each solder type. Note: These profiles may not be the optimum profile for the user's application. In no case should the temperature exceed 260C. It is recommended that the user develop a reflow profile based upon the specific application. In general, keep in mind that the lowest peak temperature and shortest dwell time above the melt temperature of the solder results in less shock and stress to the product. In addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly.
6.873 2x 0.5 BSC 16x
TP RAMP-UP CRITICAL ZONE TL TO TP
tP
TEMPERATURE
TL
TSMAX TSMIN
tL
tS
PREHEAT
RAMP-DOWN
05461-022
t25C TO PEAK
TIME
Figure 21. Recommended Solder Reflow Profiles
Table 11. Solder Profile Characteristics
Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tp) Ramp-Down Rate Time 25C to Peak Temperature Sn63/Pb37 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec 183C 60 sec to 150 sec 240C + 0C/-5C 10 sec to 30 sec 6C/sec max 6 min max
0.67 BSC 12x
1 BSC 16x 0.9315 4x
Figure 20. Second Level Assembly Pad Layout
Rev. A | Page 14 of 16
05461-018
0.9315 4x
ADIS16100 OUTLINE DIMENSIONS
8.33 8.20 SQ 8.07 1.1585 BSC
13
PIN 1 INDICATOR
16 1
PIN 1 INDICATOR
12
0.797 BSC
0.873 BSC
9 8 5 4
TOP VIEW
0.227 BSC
BOTTOM VIEW
0.373 BSC
7.00 TYP
5.20 MAX
SIDE VIEW
Figure 22. 16-Terminal Land Grid Array [LGA] (CC-16-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16100ACC ADIS16100/PCB Temperature Range -40C to +85C Package Description 16-Terminal Land Grid Array (LGA) Evaluation Board Package Option CC-16-1
Rev. A | Page 15 of 16
030906-A
ADIS16100
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05461-0-5/06(A)
Rev. A | Page 16 of 16

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Price & Availability of ADIS16100

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